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W532
Frequency Multiplying, Peak Reducing EMI Solution
Features
* Cypress PREMISTM family offering * Generates an EMI optimized clocking signal at the output * Selectable frequency range and multiplication factor * Single 1.25% or 5% center spread output * Integrated loop filter components * Operates with a 3.3V or 5V supply * Low power CMOS design * Available in 16-pin SOIC Table 1. Output Frequency Range Selection OR2 0 0 1 1 OR1 0 1 0 1 Output Range (Multiplication Factor Selection) reserved 15 MHz FIN 30 MHz 30 MHz FIN 60 MHz 60 MHz FIN 120 MHz
Table 2. Modulation Width Selection MW 0 1 Output Favg + 0.625% Fout Favg - 0.625% Favg + 2.5% Fout Favg - 2.5%
Key Specifications
Supply Voltages: ........................................VDD = 3.3V 0.3V or VDD = 5V 10% Frequency Range: .........................15 MHz Fout 120 MHz Cycle to Cycle Jitter: ......................................... 150 ps (typ.) Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time ................................... 5 ns (max.)
Table 3. Input Frequency Range Selection IR2 0 0 1 1 IR1 0 1 0 1 Input Range reserved 15 MHz FIN 30 MHz 30 MHz FIN 60 MHz 60 MHz FIN 120 MHz
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
X1 XTAL Input X2
W532
Spread Spectrum Output (EMI suppressed)
X1 X2 AVDD *OR1 NC AGND ^OR2 *SSON#
1 2 3 4 5 6
16 15 14 13 12 11 10 9
VDD GND IR1^ IR2^ SSOUT GND VDD MW*
W532
7
8
3.3V or 5.0V
Oscillator or Reference Input
X1
Notes: 1. ^ pins have internal pull-up 2. * pins have internal pull-down
W532
Spread Spectrum Output (EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor.
Cypress Semiconductor Corporation Document #: 38-07253 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 28, 2002
W532
Pin Definitions
Pin Name SSOUT CLKIN or X1 Pin No. 12 1 Pin Type O I Pin Description Output Modulated Frequency: Frequency modulated signal. Frequency of the output is selected as shown in Table 1. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: Input connection for an external crystal. If using an external reference signal, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Modulation Width Selection: When Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal (see Table 2). Reference Frequency Selector: Logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. Output Frequency Selection Bits: These pins select the frequency of operation for the output. Refer to Table 1. OR1: DOWN - OR2: UP. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: Connect all ground pins to the common ground plane. No Connect: Leave this pin floating.
NC or X2 SSON#
2 8
I I
MW
9
I
IR1:2
14, 13
I
OR1:2 VDD GND NC
4, 7 3, 10, 16 6, 11, 15 5
I P G NC
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W532
Overview
The W532 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (IR1:2, OR1:2 pins), the frequency range can be set (see Table 1 and Table 3). Spreading percentage is set with pin MW as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common.
Functional Description
The W532 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector
VDD Clock Input Freq. Divider Q Phase Detector Charge Pump
Reference Input
VCO
Post Dividers
CLKOUT (EMI suppressed)
Modulating Waveform Feedback Divider P
PLL
GND
Figure 1. Conceptual Block Diagram
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W532
Spread Spectrum Frequency Timing Generation The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. 5dB/div Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter XMOD% in the frequency spread selection table. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX - XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. SSON# Pin An internal pull-down resistor defaults the chip into spread spectrum mode. When the SSON# pin is asserted (active LOW) the spreading feature is enabled. Spreading feature is disabled when SSON# is set HIGH (VDD).
SSFTG
Typical Clock
Amplitude (dB) Figure 2. Typical Clock and SSFTG Comparison
100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100% Frequency Shift 10% 20% 30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Time
Figure 3. Modulation Waveform Profile
Document #: 38-07253 Rev. *A
100%
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W532
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 or -40 to +85 -55 to +125 0.5 Unit V C C C W
Parameter VDD, VIN TSTG TA TB PD
Description Voltage on any Pin with Respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation
DC Electrical Characteristics: 0C < TA < 70C or -40C to +85C, VDD = 3.3V 0.3V
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power-Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 150 25 Note 4 Note 4 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V 15 15 7 2.4 -50 50 2.4 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 18 Max. 32 5 0.8 Unit mA ms V V V V A A mA mA pF k
Note: 3. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 4. Inputs OR2 and IR1:2 have a pull-up resistor, Inputs SSON# OR1 and MW have a pull-down resistor.
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W532
DC Electrical Characteristics: 0C < TA < 70C or -40C to +85C, VDD = 5V 10%
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power-Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 150 25 Note 4 Note 4 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V 24 24 7 2.4 -50 50 0.7VDD 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 30 Max. 50 5 0.15VDD Unit mA ms V V V V A A mA mA pF k
AC Electrical Characteristics: TA = 0C to +70C or -40C to +85C, VDD = 3.3V 0.3V or 5V10%
Parameter fIN fOUT tR tF tOD tID tJCYC Description Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Test Condition Input Clock Spread Off VDD, 15-pF load, 0.8-2.4V VDD, 15-pF load, 2.4-0.8V 15-pF load 40 40 150 Min. 14 13 2 2 Typ. Max. 120 120 5 5 60 60 300 Unit MHz MHz ns ns % % ps
Ordering Information
Ordering Code W532 W532 Package Name G GI Package Type 16-Pin Plastic SOIC (300-mil) 16-Pin Plastic SOIC (300-mil) Temperature Range Commercial (0 - 70) Industrial (-40 - 85)
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W532
Package Diagram
16-Pin Small Outline Integrated Circuit (SOIC, 300-mil)
Document #: 38-07253 Rev. *A
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W532
Document Title: W532 Frequency Multiplying, Peak Reducing EMI Solution Document Number: 38-07253 REV. ** *A ECN NO. 110518 122695 Issue Date 01/07/02 12/28/02 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-01061 to 38-07253 Add power up requirements to maximum ratings information.
Document #: 38-07253 Rev. *A
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